1. Field of the Invention
The present invention relates to a process for testing the operation an application specific integrated circuit, as well as an application specific integrated circuit designed for implementing this process.
2. Discussion of the Related Art
Application specific integrated circuits, or ASIC (for "Application Specific Integrated Circuit") are integrated circuits made on a single chip as requested by the user.
Certain application specific integrated circuits comprise a central processing unit (for example a signal processor, or DSP, in the case of an integrated circuit dedicated to signal processing) associated with a certain number of devices which depend on the application of the circuit: memories, interfaces etc.
The user supplies the manufacturer with the application program for the circuit and information on the desired circuit configuration such as the type and volume of work memories or the nature of the circuit interface devices. The integrated circuit is then made on a chip by associating with the central processing unit, the specified devices, in particular a read-only memory (ROM) containing the application program.
Once the silicon chip forming the application specific circuit has been manufactured, various tests must be applied thereto in order to verify its correct operation. Customarily, the manufacturer of the circuit tests the makeup of the circuit (characteristics of the components, connections etc.) and the user tests his application program or the way in which the circuit executes it.
For the manufacturer's test, it is known to execute, via the central processing unit, an automatic test program stored in the program memory of the circuit. The makeup of the central processing unit can thus be tested. The makeup of certain devices associated with the central processing unit can likewise be thus tested, through a knowledge of their characteristics: type, volume, format, waveform of the signals etc. Now, in the case of an application specific integrated circuit, these characteristics are known only after receipt of the request from the user. The number of possible configurations of the circuit being very high, it is not possible to provide for an automatic test program for each configuration requested. On the contrary, it is desired that a program be able to test circuits having various configurations.
In order to test integrated circuits, it is also known, for example from EP-A-0 358 376, to use a shift register formed by connecting in series a set of elementary cells mounted on the input/output lines of the integrated circuit. Each cell can inject onto its respective line a value entered serially through the shift register, and sample the value of the signal carried by this line with a view to a serial reading through the shift register. It is thus possible to inject test signals into the integrated circuit and to check the behavior of the circuit in response to these signals. As the elementary cells are mounted at the level of the external gateways of the integrated circuit, they do not give access directly to the internal buses of the circuit serving in the communications between the central processing unit and the application-dependent devices in the case of an application specific integrated circuit. This method does not therefore allow separate testing of the central processing unit and of the application-dependent devices, without considerably increasing the number of elementary cells of the shift register, to the detriment of the compactness of the integrated circuit and of the speed of the shift register. The serial entry and reading of the data through the shift register are slow operations so that it is not possible in practice systematically to test correct operation of the devices associated with the central processing unit, in particular memories which may typically contain several hundreds of thousands of bits.
In view of the foregoing, a purpose of the present invention is to propose a process for testing the operation of an integrated circuit which is well suited to the case of application specific integrated circuits and which in particular allows the manufacturer to test both the makeup of the central processing unit and that of the application-dependent devices.
Another purpose of the invention is that the process offers facilities for testing the application program of the application specific integrated circuit.
The invention thus proposes a process for testing the operation of an application specific integrated circuit comprising a central processing unit and devices which are dependent on the application of the integrated circuit and are connected to the central processing unit, in which at least one shift register is formed by connecting in series a set of elementary cells each mounted on a respective line carrying a binary signal of the integrated circuit, each cell being able to inject onto the said line a value entered serially through the shift register and being able to sample the value of the binary signal carried by the said line with a view to a reading of this value through the shift register wherein the elementary cells of the shift register are mounted on lines corresponding to gateways of the central processing unit.
It is thus possible, by virtue of a shift register which keeps a relatively simple structure and simple organization, to test both the central processing unit and the associated devices. The register can achieve this with a restricted number of elementary cells, some of them being mounted on the internal buses of the circuit connecting the central processing unit to the associated devices.
It will be noted that the making of application specific integrated circuits derives substantial advantages from the implementation of the process according to the invention. Indeed, in order to rationalize their design and manufacture, it is customarily desirable for the circuits to be designed by assembling somewhat standardized units: central processing unit, memory unit(s), interface unit(s), etc, it being possible for the user to choose these units from "libraries" offered by the manufacturer. The classical mounting of a shift register at the level of the external terminals of the overall integrated circuit does not allow standardization of the structure of this register, which will always depend on the particular configuration of the circuit. Through the invention, this register can be included within a standardized central processing unit usable with a large number of configurations of associated devices. A step of design and optimization of surface area of the shift register, with each request for an application specific integrated circuit, is therefore avoided.
A preferred version of the process according to the invention includes a procedure for automatic testing of the makeup of the integrated circuit comprising the following steps:
entry through the shift register of characteristic data of the devices which are dependent on the application and are connected to the central processing unit and storage of these characteristic data; PA1 execution by the central processing unit of a test program stored in a program memory of the integrated circuit, this test program including at least one instruction for reading the said characteristic data and one instruction for storing test results; and PA1 reading of the test results stored through the shift register. PA1 entry through the shift register of a verification address, and storage of this verification address; PA1 execution of the application program as far as the instruction stored in the said verification address in the program memory; and PA1 reading through the shift register of values present on the access lines of the central processing unit.
The makeup of the circuit can then be tested in a fast way by executing a test program which receives certain configuration parameters via the shift register, the results of this program being also read by the shift register. The execution proper of the test program is not delayed by serial data exchanges through the shift register, so that the procedure makes it possible to test both the logic of the circuit and the speed of execution of the instructions.
Preferably, the process according to the invention includes a procedure for testing an application program stored in a program memory of the integrated circuit, this procedure comprising the following steps:
The user of the integrated circuit can thus test his application program and conveniently detect possible improvements to be made thereto ( emulation mode ).
The verification address is advantageously stored in elementary cells of the shift register which are mounted on lines of an instruction address bus of the central processing unit, provided in order to tag the locations of the program memory containing the instructions of the application program.
This avoids provision for a memory zone serving uniquely in the storage of the verification address.
A second aspect of the invention concerns an application specific integrated circuit, comprising a central processing unit, and devices which are dependent on the application of the integrated circuit and are connected to the central processing unit, and at least one shift register including a set of elementary cells connected in series and each mounted on a respective line carrying a binary signal of the integrated circuit, each cell being able to inject onto the said line a value entered serially through the shift register and being able to sample the value of the binary signal carried by the said line with a view to a reading of this value through the shift register wherein the elementary cells of the shift register are mounted on lines corresponding to gateways of the central processing unit.
This circuit is designed to implement the above process.